In the manufacture of semiconductor wafers, plasma etching is a process for transferring circuit patterns from the surface of a semiconductor wafer to an underlying layer by using a highly reactive ionized gas to remove unmasked portions of the wafer. As in most manufacturing processes, quality control of a desired product attribute is necessary. In integrated circuit (“IC”) manufacturing a key wafer attribute is the post etch thickness of a film on the wafer. Over etching can adversely effect the performance of the final device.
Plasma etching devices for processing wafers are well known. A typical plasma etching apparatus includes a process chamber for processing a substrate by etching. A chuck usually serves as a lower electrode in the process chamber, which can be set in a vacuum state. A lower electrode is typically configured to include an electrostatically attracting electrode for holding the substrate by action of an electrostatic attraction, an insulating plate provided under the electrode, and a lower electrode body provided under the insulating plate. The wafer is generally placed on and fixed to the chuck, and then subjected to the plasma etching process.
There are two commonly utilized techniques for fixing a wafer to a chuck, including mechanical supporting means such as a clamp, and an electrostatic chuck for attaching a wafer by means of an electrostatic attractive force. A typical electrostatic chuck includes a metallic base plate that is coated with a thick layer of slightly conductive dielectric material. A silicon wafer of approximately the same size as the chuck is placed on top of the chuck and a potential difference is applied between the silicon wafer and the base plate of the electrostatic chuck. This causes an electrostatic attraction proportional to the square of the electric field in the gap between the silicon wafer and the chuck face.
When the chuck is used in a plasma filled chamber, the electric potential of the wafer tends to be fixed by the effective potential of the plasma. The purpose of the dielectric layer on the chuck is to prevent the silicon wafer from coming into direct electrical contact with the metallic part of the chuck and shorting out the potential difference. On the other hand, a small amount of conductivity appears to be desirable in the dielectric coating so that much of its free surface between points of contact with the silicon wafer is maintained near the potential of the metallic base plate; otherwise, a much larger potential difference would be needed to produce a sufficiently large electric field in the vacuum gap between the wafer and chuck.
During plasma etching of pattern wafers, the plasma raises the temperature of the wafer to an undesirable level that could damage the wafer. Accordingly, the chuck must be kept as cool as possible. The current preferred method of cooling a plasma chuck is with conductive cooling of the backside of the chuck through the use of helium. The face of the chuck generally includes a pattern of grooves in which helium gas is maintained. This gas provides cooling by thermal contact between the wafer and the chuck. To contain the helium at the chuck and prevent it from escaping into the reaction, a clamp must be incorporated with the chuck to hold the wafer down.
Based on the foregoing it can thus be appreciated that in a process for manufacturing a semiconductor device, plasma can be generated in a process chamber, and a target object such as a semiconductor wafer can be subjected in the atmosphere of the plasma to various types of plasma processes including an etching process. The typical plasma etching apparatus for etching a semiconductor wafer generally includes a process chamber containing a lower electrode for placing the wafer thereon and an upper electrode opposed to the lower electrode.
At the time of performing the etching process, a process gas can be introduced into the process chamber, which is exhausted beforehand and has its inside set to a reduced-pressure atmosphere. Thereafter, an RF power can be applied to at least one of the lower and upper electrodes. As a result, the process gas is converted into plasma. Using this plasma, the target object or wafer may be appropriately etched.
In modern VLSI design and fabrication, the position of a semiconductor wafer on a lower electrode is thus of paramount importance, particular in plasma etching operations. The position of such a wafer on a lower electrode is a factor that significantly influences etching rate and particle development. A wafer shift on a lower electrode can result in over/under etching. Additionally, such a wafer shift can cause the plasma to directly damage the lower electrode and cause particle containment.
Two major systems and/or techniques are currently utilized to clamp the wafer for heat exchange with helium flow between a wafer back-side and a lower electrode. One method and/or system involves the utilization of a clamp device. The other method and/or system is an ESC-based system, well known in the plasma etching arts. In addition to being utilized as a medium back side helium (B/H) flow has been utilized as an index for monitoring the position of a wafer on a lower electrode. Some processes do not require cooling to maintain the wafer temperature. Additionally, detectors or sensors currently do not exist which can pre-warn regarding wafer shifts on a lower electrode.
Based on the foregoing, the present inventors have concluded that a need exists for a method and apparatus which would permit in-situ measurement of the position of a semiconductor wafer on a lower electrode utilized in a process chamber for plasma etching operations. The present inventors thus believe that the method and apparatus disclosed herein solves this important need.